pccx v002 Architecture

Parallel Compute Core eXecutor — Second Generation

pccx v002 is the second generation of a heterogeneous NPU architecture designed to accelerate autoregressive decoding of Transformer-based large language models (LLMs) on edge devices. It takes a hard look at the GEMM-centric v001 design and restructures the data path around a single shared activation bus: GEMV, CVO, and GEMM now pull activations from the same L2 cache, which sits at the geometric center of the floorplan. The result is shorter, more regular data movement across every compute path.

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Overview

• Overview
  • 1. Project Goal
  • 2. Target Workload
  • 3. Key Differences from v001
  • 4. Ecosystem Layers
  • 5. Documentation Map

Hardware Architecture

• Hardware Architecture
  • Design Rationale: v001 → v002
  • Top-Level Architecture
  • Physical Floorplan
  • Memory Hierarchy
  • KV Cache Optimization Strategy
  • GEMM Core (Systolic Array)
  • GEMV Core
  • SFU Core (Complex Vector Operations)
  • DSP48E2 W4A8 Bit Packing and Sign Recovery

Instruction Set Architecture (ISA)

• Instruction Set Architecture (ISA)
  • Instruction Encoding
  • Per-Instruction Encoding
  • Per-Instruction Dataflow

Software Stack

• Software Stack
  • C API Overview

Target Models

• Target Models
  • Gemma 3N E4B — Overview
  • Gemma 3N E4B — Operator-Level Pipeline
  • Gemma 3N — Attention and RoPE Constraints
  • Gemma 3N — LAuReL and PLE Calibration Modules
  • Gemma 3N — FFN Gaussian Top-K Sparsity
  • Gemma 3N E4B on pccx v002 — Execution and Scheduling

RTL Source

• RTL Source Reference (v002)
  • ISA Type Package
  • NPU Top-Level
  • Compute Core Modules
  • NPU Controller Modules

Verification

• Verification
  • 1. Current test suite
  • 2. Gaps (tracked as open items)
  • 3. Planned scope (system level)