RTL Source Reference (v001)¶
This section is the authoritative browser for every SystemVerilog module
that makes up the archived v001 NPU (64 files across 8 categories, plus
the host-side C API). Every file under codes/v001/ is reachable from
here via a language-aware literalinclude — click through to read
the real source with syntax highlighting; no separate repository visit
required.
See also
- pccx: Parallel Compute Core eXecutor
High-level block diagram and core roles.
- pccx ISA Specification
64-bit VLIW instruction set backing this RTL.
v001 is frozen. Active RTL is in hwkim-dev/pccx-FPGA-NPU-LLM-kv260 and documented under RTL Source Reference (v002).
NPU_top wrapper, BF16 barrel shifter.
ISA package, device / type / arch packages, interface defs.
AXI-Lite frontend, decoder, dispatcher, global scheduler.
32×32 systolic array with DSP48E2 MACs.
Parallel μV-cores with reduction tree.
Softmax / GELU / CORDIC non-linear engine.
L2 URAM cache, dispatcher, HP buffers, CVO bridge.
Feature-map cache + BF16→fixed-point pipeline.
BF16 math, general algorithms, FIFO queue primitives.
pccx_v1 HAL + high-level C interface under sw/driver/.