Hardware Architecture

The pccx v002 hardware is organized along three axes: a top-level interconnect, a set of heterogeneous compute cores, and a hierarchical memory subsystem. This section walks through the design rationale and the microarchitecture of each piece.

Design Rationale

• Design Rationale: v001 → v002

System View

• Top-Level Architecture
• Physical Floorplan
• Memory Hierarchy
• KV Cache Optimization Strategy

Compute Cores

• GEMM Core (Systolic Array)
• GEMV Core
• SFU Core (Complex Vector Operations)

Numerical Techniques

• DSP48E2 W4A8 Bit Packing and Sign Recovery